The present invention relates to electrical circuits and more particularly to a dual-stage digital-to-analog converter.
A digital-to-analog converter (DAC) converts a digital input, which can include one or more bits of data, into an analog output signal functionally related to the digital input data. A DAC is typically implemented in an integrated circuit or chip, although it can be implemented on a circuit board by an appropriate arrangement of components. DACs further can be utilized in a variety of applications, such as instrumentation applications, level detection applications, drivers for LCD screens, servo tracking, disk drives and communications applications.
A common type of DAC is a linear DAC that generates an analog output signal that varies linearly with respect to the value of the digital input signal. By way of example, a single resistor string voltage scaling DAC produces an analog voltage from a digital word by selectively tapping a voltage-divider resistor string connected between a high and a low voltage reference voltage. Typically, the voltage drop across each resistor is equal to one least significant bit (LSB) of output voltage range.
A dual resistor string DAC, generally referred to as a two-stage cascaded converter, converts a digital word into a corresponding analog signal employing two-cascaded resistor strings. The first stage or resistor string is coupled across two supply voltages, such as a reference voltage and ground. The first resistor string resolves higher order bits of the digital input or control word by selecting one resistor from the first resistor string producing a voltage based on the most significant bits (MSB) of the digital word. The voltage produced by the first resistor string is applied to the ends of a second stage or resistor string. The second resistor string resolves lower order bits of the digital word by selecting a tap of one resistor from the second resistor string via switches based on the least significant bits (LSB) of the digital word. The second resistor string produces an output effectively interpolating the selected first stage segment voltage in accordance with the lower order bits.
FIG. 1 illustrates a conventional dual-stage resistor string DAC system 10. The DAC system 10 includes a first half coarse string (A) 14 and a second half coarse string (B) 16 coupled through a midpoint (MID) 15. The first half coarse sting 14 is coupled to an output of an input amplifier 12. The second half coarse string 16 is coupled to ground through a resistor R3 via a node 17. The input amplifier 12 receives a reference voltage VREF at a positive input terminal and provides the reference voltage VREF at the midpoint 15 via a negative input terminal. The voltage VREF at the midpoint 15 causes a current to flow through the resistors of the second half coarse string 16 and the resistor R3 to ground through the node 17. The same current flows through the first half coarse string 14 causing a voltage VHIGH to be provided at the output of the input amplifier 12. This provides a voltage drop VDROP from the first half coarse string 14 to the midpoint 15 and a similar voltage drop VDROP from the midpoint 15 to the node 17 across the second half coarse string 16. Therefore, the range of the DAC system is set to be VREF+/xe2x88x92VDROP. For example, if the voltage reference VREF was selected to be two volts and the resistor R3 was selected such that a voltage drop across the resistor R3 was one volt, then the voltage VHIGH would be at three volts. Other ranges can be provided by varying the selection Of VREF and R3.
A first output of the first half coarse string 14 and a first output of the second half coarse string 16 are coupled to a first input of a fine string 18 via switches SA and SB. A second output of the first half coarse string 14 and a second output of the second half coarse string 16 are coupled to a second input of the fine string 18 via switches SA and SB. A MSB control signal (MSBCTL) is provided to both the first half coarse string 14 and the second half coarse string 16. A resistor or segment voltage from one of the first half coarse string 14 and the second half coarse string 16 is selected via internal switches to provide a desire output voltage to the fine string 18 based on the MSB control signal. If the resistor selected is in the first half coarse string 14, then the switches SA are closed and the switches SB are opened. If the resistor selected is in the second half coarse string 16, then the switches SB are closed and the switches SA are opened. A tap from a resistor in the fine string 18 is then selected based on a LSB control signal (LSBCTL) to provide an analog voltage signal at a tap output of the fine string 18.
The analog voltage signal at the tap output is provided to a positive input terminal of an output amplifier 20. The output (DACOUT) of the output amplifier 20 corresponds to the analog voltage associated with the MSB and LSB of the digital word provided as input to the DAC system 10. A first gain switch SG1 is provided that allows selection of the DACOUT to have unity gain such that the output DACOUT is equal to VREF+/xe2x88x92VDROP. A second gain switch SGN is provided that allows a user to provide a gain to the tap output signal such that the output DACOUT is equal VREF+/xe2x88x92N*VDROP, where N is the gain provided by the amplifier 20. The selected gain depends on the selection of a resistor R1 coupled between the negative terminal of the output amplifier 20 and the output of the output amplifier 20, and a resistor R2 coupled between the resistor R1 and the reference voltage VREF. Other switches and resistor configurations can be employed to provide different gains.
The input amplifier 12 and the output amplifier 20 have offset voltage associated therewith and require trimming in order for the DAC system 10 to provide accurate conversion. The offset voltage is also amplified along with the output signal if the gain of the output amplifier is selected to provide a gain greater than unity. The offset voltage and any gain of the offset voltage is undesirable.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a dual-stage DAC system and a method of digital-to analog conversion. The dual-stage DAC system includes a coarse resistor network coupled to a fine resistor network. The coarse resistor network includes a first portion and a second portion that provide a plurality of segment voltages. A segment voltage is selected from one of the first portion and the second portion based on a first set of control bits. The fine resistor network provides a tap output voltage selected from a plurality of tap output voltages that correspond to the selected segment voltage. The selected tap output voltage is selected from the fine resistor network based on a second set of control bits. The output of the fine resistor network is provided to an amplifier that sets a reference voltage and buffers the selected tap output voltage. A predetermined current is coupled to one of the first portion and the second portion of the coarse resistor network based on the state of the first set of control bits and/or the segment voltage selected.
In another aspect of the present invention, a dual-stage DAC system is provided that includes a coarse resistor having a first portion and a second portion that provide a plurality of segment voltages. A segment voltage is selected from one of the first portion and the second portion based on a state of a sampled data word. The selected segment voltage is provided to a fine resistor network that provides a selected tap output voltage selected from a plurality of tap output voltages based on the state of the sampled data word. The output of the fine resistor network is provided to an amplifier that receives the selected tap output voltage and provides a DAC system output voltage. The amplifier is configured as one of a non-inverting amplifier and a voltage follower amplifier based on the state of the sampled data word.
In yet another aspect of the present invention, segment voltages provided by the first portion of the coarse resistor network are above a reference voltage and segment voltages provided by the second portion of the coarse resistor network are below the reference voltage. The reference voltage can be set to an intermediate voltage (e.g., midpoint output voltage) associated with the output voltage of the DAC system. Additionally, the first set of control bits can be associated with a MSB of a sampled data word and the second set of control bits can be associated with a LSB of the sampled data word.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.